Jiangjiang Gu has led the development of a nanowire transistor that breaks the speed and energy-efficiency barrier imposed by the use of silicon in conventional transistors and allow far more powerful and less-expensive computers.
The new transistor is fabricated from nanowires grown from indium-gallium-arsenide which conducts electrons five times faster than silicon, allowing for both more speed, compactness and far more energy efficiency. Because it also generate less waste heat, surrounding components don’t have to use costly heat-resistant materials. Indium-gallium-arsenide is a so-called III-V compound because it combines elements from the third and fifth groups of the periodic table.
Gu’s new transistor also uses the so-called 3-D vertical structure that will be the industry standard beginning in 2012.
“Industry and academia are racing to develop transistors from the III-V materials,” said Peide “Peter” Ye, the Purdue electrical engineering and computer science professor under whose supervision Purdue doctoral student Gu was working, along with Harvard doctoral student Yiqun Liu and Harvard chemistry professor Roy Gordon. “Here, we have made the world’s first 3-D gate-all-around transistor on much higher-mobility material than silicon, the indium-gallium-arsenide.”
Gu and colleagues applied a dielectric coating made of aluminum oxide using a method called atomic layer deposition. Atomic layer deposition is commonly used in industry, which means the new design can be produced relatively inexpensively using existing production equipment.
“A thinner dielectric layer means speed goes up and voltage requirements go down,” Ye explained.
The efficiency of a transistor depends on the speed of its gates, the switches that must turn current on and off rapidly as digital computations take place. Current generation of chips contain gates of about 45 nanometers. In 2012 22-nanometer silicon-based 3-D transistors are being rolled out. Transistor layout had to be changed from today’s flat structure to the vertical structure because 22-nanometer gates can’t function in a flat design.
“Once you shrink gate lengths down to 22 nanometers on silicon you have to do more complicated structure design,” Ye said. ”The ideal gate is a necklike, gate-all-around structure so that the gate surrounds the transistor on all sides.”
Gu’s group coated the indium-gallium-arsenide nanowires with a “dielectric” which acts as a gate. By 2015 conventional silicon-based transistors are expected to reach a gate length of 14 nanometers — the theoretical limit of silicon due to the leakage of current. But nanowires made of III-V alloys — like the indium-gallium-arsenide compound used by Gu’s group — can remain efficient down to the 10 nanometer range, with the attendant speed and energy-efficiency advantages.
The group presented their work in a paper during the International Electron Devices Meeting on Dec. 5-7 in Washington, D.C.
Their work is funded by the National Science Foundation and the Semiconductor Research Corp. and is based at the Birck Nanotechnology Center in Purdue’s Discovery Park. In 2009 Ye’s group had reported a transistor advance called finFET, for fin field-effect transistor which uses a finlike structure instead of the conventional flat design. The new design uses nanowires instead of the fin design.
Jiangjiang Gu earned his bachelors degree from Shanghai Jiaotung University.
